1. Field of the Invention
The present invention relates to testing of replicated (i.e., identical) components of an electronic device. Although the present invention will be described in connection with testing of replicated electronic components of a parallel processor integrated circuit, other utilities are also contemplated for the present invention, including use in testing of replicated electronic components in other types of electronic devices and systems.
2. Brief Description of Related Prior Art
A parallel processor computer system may be implemented using a number of replicated central processing units (CPUs) or processors to perform certain tasks in parallel. Such a parallel processor computer system may be fabricated as a single application specific integrated circuit (ASIC) chip exhibiting a relatively high degree of on-chip circuit integration. Unfortunately, this high degree of integration can make it difficult and is time consuming to test the chips"" replicated CPUs for defects.
One partial solution to this problem has been to include among the features of the parallel processor ASIC, on-chip systems for facilitating testing of the replicated CPUs after manufacture, but prior to supply of the ASIC to its intended end user. One such conventional on-chip system includes respective on-chip serial interfaces by which test clock signals, test control signals and serial test vectors (hereinafter collectively referred to as xe2x80x9ctest inputsxe2x80x9d) may be input, in parallel, from off-chip test logic to respective serial scan test circuitry comprised in the respective parallel processor CPUs, and also by which the serial test output signals (hereinafter xe2x80x9ctest outputsxe2x80x9d) generated by the CPUs in response to the test inputs may be supplied, in parallel, to the off-chip test logic. The off-chip test logic compares the actual test outputs received from the chip to predetermined values that are expected for same if the CPUs are operating normally (i.e., there are no manufacturing or design defects in the CPUs). Depending upon the degree to which the actual test outputs conform to the values expected for same, the off-chip test logic will indicate either that the parallel processor chip has passed the test (i.e., no defects were determined by the logic to be present in the CPUs of the chip), or has failed the test (i.e., defects are present in one or more of the CPUs).
Unfortunately, although this conventional testing technique permits the amount of time necessary to carry out testing of the ASIC""s CPUs to be substantially reduced, it also requires a number of serial test interfaces equal to the number of CPUs in the ASIC being tested. Thus, since each respective serial test interfaces typically includes multiple respective external test interface pins (e.g., to propagate respective test inputs to the respective CPU connected to the respective interface), the number of external test interface pins required to implement this technique is equal to N * P, wherein N represents the number of CPUs of the parallel processor chip being tested, and P represents the number of external test interface pins in each serial test interface. Disadvantageously, the relatively large number of test pins required to implement this technique consumes an undesirably large amount of parallel processor chip I/O pins.
A second such conventional testing technique involves coupling the respective serial scan test circuitry of the individual CPUs together to form, in essence, a single serial scan test chain connected to a single on-chip serial test interface. This second conventional testing technique has the advantage that the number of external test interface pins required to implement this technique is much less than is required to implement the first conventional technique described above. That is, since only a single interface is required to implement this second conventional testing technique, the number of external test interface pins required to implement this second technique may be reduced by a factor of N compared to the first conventional technique. Disadvantageously, however, more time is required to carry out testing of the chip using the second technique than is required to carry out such testing using the first technique. This is because, in the second technique, the scan chain used to carry out testing has a length that is, in essence, equal to the sum of the lengths of each of the scan chains of the respective CPUs. Thus, as can be readily appreciated, the time required to propagate the test inputs and outputs through the scan chain used in the second technique is substantially greater than the time required to propagate the test inputs and outputs, in parallel, through each of the CPUs"" scan chains, as in the first technique.
In a modification of the second conventional technique, a single serial scan test chain is not formed, but rather, multiplexer circuitry is provided to permit each of the individual CPUs to be separately, sequentially tested via the single test interface, using each respective CPU""s scan test chain separately. Unfortunately, this modification of the second conventional technique suffers from the aforesaid disadvantages of the second conventional technique.
Thus, it would be desirable to provide a technique for testing the replicated CPUs of a parallel processor chip that is able to achieve the advantages of the conventional testing techniques described above, without suffering from the disadvantages of these conventional techniques. More specifically, it would be desirable to provide a technique for testing the replicated CPUs of a parallel processor chip that is able to carry out such testing in a time substantially equal to that required by the first conventional technique, but that can be implemented using fewer external test interface pins than are required to implement the first conventional technique (i.e., fewer than N*P).
In accordance with the present invention, a testing technique is provided that may be used to test the replicated CPUs of a parallel processor, and that is able to achieve the advantages of the aforedescribed conventional testing techniques, without suffering from the disadvantages of said conventional techniques.
In broad concept, in one aspect of the testing technique of the present invention, the same test inputs may be broadcast, in parallel, from a single test interface (e.g., an external serial test interface) to (e.g., respective scan test chains of) each of the replicated components (e.g., replicated CPUs) of the electronic device (e.g., the parallel processor ASIC chip) under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the interface, that compares the respective test outputs to each other and generates a fault signal if (e.g., all) corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface to indicate to an external testing device that one or more of the replicated components may be defective.
In another aspect of the present invention which may be practiced either alone or in conjunction with the first aspect of the present invention, a multiplexer may be provided in the electronic device to receive, in parallel, the respective test outputs from the replicated components, and to supply selected test outputs of a selected one of the replicated components to an external pin of the test interface, based upon a selection signal received from test control circuitry comprised in the test interface. A special register comprised in the test control circuitry may be loaded, based upon test control signals supplied to the circuitry, with a data value indicative of which of the test outputs is to be output to the external pin. The selection signal supplied to the multiplexer may be generated based upon the data value loaded into the special register.
Thus, according to the present invention, only a single external test interface may be required to test the replicated components of an electronic device, and this interface need only include a single additional external interface pin (i.e., the pin for propagating the fault signal) compared to the aforesaid prior art external test interfaces. Also in the present invention, propagation of test inputs to each of the replicated components from the test interface, and propagation of the test outputs from each of the replicated components to the test interface, respectively, may take place in parallel. Thus, advantageously, when the testing technique of the present invention is used to test the replicated CPUs of a parallel processor, such testing (1) may be carried out in a time substantially equal to that required by the first conventional technique and (2) may be implemented using fewer external test interface pins than are required to implement the first conventional technique (i.e., fewer than N*P).
The aforesaid and other features and advantages of the present invention will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and in which: